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The z15 is a microprocessor made by IBM for their z15 mainframe computers, announced on September 12, 2019.cite-ref-ibmpress-2-0[2]

• Description

• References

The processor unit chip (PU chip) has 12 cores. The z15 cores support two-way simultaneous multithreading.cite-ref-redbooktechspec-3-0[3]

The cores implement the CISC z/Architecture with a superscalar, out-of-order pipeline. New in z15 is an on-chip nest accelerator unit, shared by all cores, to accelerate compression.cite-ref-redbooktechspec-3-1[3]

The cache (e.g. level 3) is doubled from the previous generation z14, while the "L4 cache increased from 672MB to 960MB, or +43%" with the new add-on chip system controller (SC) SCM. Both it and all levels of cache in the main processor from level 1 use eDRAM, instead of the traditionally used SRAM. "A five-CPC drawer system has 4800 MB (5 x 960 MB) of shared L4 cache."

cite-note-z15-data-sheet-11. "IBM z15 (z15)". IBM. Archived from the original on 2020-04-20.

cite-note-ibmpress-22. ↑ "IBM Unveils z15 With Industry-First Data Privacy Capabilities" (Press release). IBM. September 12, 2019. Archived from the original on 2020-01-01. Retrieved 2019-09-15.

cite-note-redbooktechspec-33. ↑ IBM z15 (8561) Technical Guide (PDF). September 2019. SG24-8851-00. Retrieved September 14, 2019.